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HM514170C Series HM51S4170C Series
262,144-word x 16-bit Dynamic Random Access Memory
Rev. 1.0 Jul. 21, 1995
Description
The Hitachi HM51(S)4170C are CMOS dynamic RAM organized as 262,144-word x 16-bit. HM51(S)4170C have realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4170C offer fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4170C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4170C self refresh operation.
Features
* * * Single 5 V (10%) High speed -- Access time: 70 ns/80 ns (max) Low power dissipation -- Active mode: 660 mW/578 mW (max) -- Standby mode: 11 mW (max) 1.1 mW (max) (L-version) Fast page mode capability 1024 refresh cycles: 16 ms 128 ms (L-version) 2 WE-byte control 2 variations of refresh -- RAS-only refresh -- CAS-before-RAS refresh Battery backup operation (L-version) Self refresh operation (HM51S4170C)
* * * *
* *
HM514170C, HM51S4170C Series
Ordering Information
Type No. HM514170CJ-7 HM514170CJ-8 HM514170CLJ-7 HM514170CLJ-8 HM51S4170CJ-7 HM51S4170CJ-8 HM51S4170CLJ-7 HM51S4170CLJ-8 HM514170CTT-7 HM514170CTT-8 HM514170CLTT-7 HM514170CLTT-8 HM51S4170CTT-7 HM51S4170CTT-8 HM51S4170CLTT-7 HM51S4170CLTT-8 Access Time 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 400-mil 44-pin plastic TSOPII (TTP-44/40DB) Package 400-mil 40-pin plastic SOJ (CP-40DA)
2
HM514170C, HM51S4170C Series
Pin Arrangement
HM514170CJ/CLJ Series HM51S4170CJ/CLJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC LWE UWE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC CAS OE A8 A7 A6 A5 A4 VSS HM514170CTT/CLTT Series HM51S4170CTT/CLTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8
(Top view)
NC LWE UWE RAS A9 A0 A1 A2 A3 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23 (Top view)
NC NC CAS OE A8 A7 A6 A5 A4 VSS
Pin Description
Pin Name A0 - A9 Function Address input - Row address A0 - A9 - Column address A0 - A7 - Refresh address A0 - A9 Data-in/data-out Row address strobe Column address strobe Read/write enable Output enable Power (+5 V) Ground No connection
I/O0 - I/O15 RAS CAS UWE / LWE OE VCC VSS NC
3
HM514170C, HM51S4170C Series
Block Diagram
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
Row Decoder
Row Row Decoder Decoder
Row Decoder
Row Decoder
Row Row Decoder Decoder
Row Decoder
Selector
Selector
Selector
Selector
I/O4
I/O4 Buffer I/O5 Buffer I/O6 Buffer I/O7 Buffer
256 k Memory Array Mat
I/O11 Buffer
Peripheral Circuit
I/O3 I/O3 Buffer
I/O2 I/O2 Buffer
I/O1 I/O1 Buffer
I/O0 I/O0 Buffer
I/O15 I/O15 Buffer
I/O14 I/O14 Buffer
I/O13 I/O13 Buffer
I/O12 I/O12 Buffer
I/O11
I/O5
I/O10 I/O10 Buffer I/O9 Buffer I/O8 Buffer I/O9
I/O6
I/O7
I/O8
LWE UWE RAS Address A9
Peripheral Circuit
CAS OE
A0,A1,A2,A3
Address A4,A5
A6,A7,A8
Selector
Row Decoder
Selector
Row Decoder
Selector
Row Decoder
Selector
Row Decoder
Row Row Decoder Decoder
Row Row Decoder Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
Operation Mode
The HM51(S)4170C series has the following 11 operation modes.
4
256 k Memory Array Mat
Peripheral Circuit
HM514170C, HM51S4170C Series
1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle (HM51S4170C) 8. Fast page mode read cycle 9. Fast page mode early write cycle 10. Fast page mode delayed write cycle 11. Fast page mode read-modify-write cycle
Inputs RAS H H L L L L L H to L L L L L CAS H L L L L L H L H to L H to L H to L H to L UWE D H H L L
*2 *2
LWE D H H L L
*2 *2
Output Open Valid Valid Open Undefined Valid Open Open Valid Open Undefined Valid
Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Self refresh cycle (HM51S4170C) Fast page mode read cycle Fast page mode early write cycle Fast page mode delayed write cycle Fast page mode read modify-write cycle
H to L D D H L L
*2 *2
H to L D D H L L
*2 *2
H to L
H to L
Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delay write cycle 3. Mode is determined by the OR function of the UWE and LWE. (Mode is set by the earliest of UWE and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However write OPERATION and output HIZ control are done independently by each UWE, LWE.
5
HM514170C, HM51S4170C Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage VIH VIL Min 0 4.5 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.5 6.5 0.8 Unit V V V V Note 2 1, 2 1 1
Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM514170C, HM51S4170C -7 Parameter Operating current Standby current
*1, *2
-8 Max 120 2 Min -- -- Max 105 2 Unit mA mA Test Conditions RAS, CAS cycling t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS, UWE, LWE, OE VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS, OE, UWE, LWE VCC - 0.2 V Dout = High t RC = min
Symbol Min I CC1 I CC2 -- --
--
1
--
1
mA
Standby current (L-version)
I CC2
--
200
--
200
A
RAS-only refresh current*2 I CC3
--
120
--
100
mA
6
HM514170C, HM51S4170C Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont)
HM514170C, HM51S4170C -7 Parameter Standby current
*1
-8 Max 5 120 130 300 Min -- -- -- -- Max 5 100 120 300 Unit mA mA mA A Test Conditions RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 125 s t RAS 1 s, CAS = VIL UWE, LWE, OE = VIH CMOS interface RAS, CAS 0.2 V, Dout = High-Z CMOS interface RAS, CAS 0.2 V, Dout = High-Z 0 V Vin 6.5 V 0 V Vout 6.5 V Dout = disable High Iout = -5.0 mA Low Iout = 4.2 mA
Symbol Min I CC5 I CC6 -- -- -- --
CAS-before-RAS refresh current*2
Fast page mode current *1, *3 I CC7 Battery backup current I CC10 (Standby with CBR refresh) (L-version)
*4
Self-refresh mode current (HM51S4170C) Self-refresh mode current (HM51S4170CL) Input leakage current Output leakage current Output high voltage Output low voltage
I CC11
--
1
--
1
mA
I CC11
--
200
--
200
A
I LI I LO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH V CC - 0.2 V, 0 V IL 0.2 V, Address can be changed once or less while RAS = VIL 5. All the V CC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage.
Capacitance (Ta = 25C, VCC = 5 V 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 10 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
7
HM514170C, HM51S4170C Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *14, *15, *17, *18
Test Conditions Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Input levels: 0 V, 3 V Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)
HM514170C, HM51S4170C -7 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol Min t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT t REF t REF 130 50 70 20 0 10 0 15 20 15 20 70 15 20 0 0 3 -- -- Max -- -- -8 Min 150 60 Max -- -- Unit ns ns Notes
10000 80 10000 20 -- -- -- -- 50 35 -- -- -- -- -- -- 50 16 128 0 10 0 15 20 15 20 80 15 20 0 0 3 -- --
10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 16 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7 23 8 9 22
8
HM514170C, HM51S4170C Series
Read Cycle
HM514170C, HM51S4170C -7 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol Min t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t OFF1 t OFF2 t CDD -- -- -- -- 0 0 0 35 0 0 15 Max 70 20 35 20 -- -- -- -- 15 15 -- -8 Min -- -- -- -- 0 0 0 40 0 0 15 Max 80 20 40 20 -- -- -- -- 15 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns 6 6 Notes 2, 3 3, 4, 13 3, 5, 13 22 20 16, 19 16
Write Cycle
HM514170C, HM51S4170C -7 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time CAS to OE delay time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH t COD 0 15 10 20 20 0 15 -- Max -- -- -- -- -- -- -- 0 -8 Min 0 15 10 20 20 0 15 -- Max -- -- -- -- -- -- -- 0 Unit ns ns ns ns ns ns ns ns Notes 10, 19 20 21 21 21 11, 21 11, 21 22
9
HM514170C, HM51S4170C Series
Read-Modify-Write Cycle
HM514170C, HM51S4170C -7 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 180 95 45 60 20 Max -- -- -- -- -- -8 Min 200 105 45 65 20 Max -- -- -- -- -- Unit ns ns ns ns ns 10, 19 10, 19 10, 19 21 Notes
Refresh Cycle
HM514170C, HM51S4170C -7 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol Min t CSR t CHR t RPC t CPN 10 10 10 10 Max -- -- -- -- -8 Min 10 10 10 10 Max -- -- -- -- Unit ns ns ns ns Notes 19 20 19
Fast Page Mode Cycle
HM514170C, HM51S4170C -7 Parameter Fast page mode cycle time Fast page mode CAS precharge time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Fast page mode read-modify-write cycle CAS precharge to UWE, LWE delay time Fast page mode read-modify-write cycle time Symbol Min t PC t CP t RASC t ACP t RHCP t CPW t PCM 45 10 -- -- 40 65 95 Max -- -- -8 Min 50 10 Max -- -- Unit ns ns 12 3, 13 Notes
100000 -- 40 -- -- -- -- 45 70 100
100000 ns 45 -- -- -- ns ns ns ns
21
10
HM514170C, HM51S4170C Series
Self refresh Mode
HM51S4170C -7 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol Min t RASS t RPS t CHS 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit s ns ns Notes 23, 24, 25
Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD t RWD (min), tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modifywrite and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP. 14. After power up pause for 100 s, then DRAM initialization requires a minimum of eight RAS only refresh or eight CAS-before-RAS refresh cycles. If the user will implement CAS-beforeRAS timing in their system, then the eight initialization cycles MUST be CAS-before-RAS cycles 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 18. A word of data can be written only when UWE and LWE go low at the same time. This implies that early write cycles cannot be combined with delayed write cycles in the same cycles because all data is latched at the fall of the first WE. In other words, staggering the WE signals in one cycle is not permitted. 19. t RCH, t RRH, t WCS , t RWD, t CWD and t AWD are determined by the earlier falling edge of UWE and LWE. 20. t WCH and t RCS are determined by the later rising edge of UWE or LWE. 21. t WP, t RWL, t CWL, t OEH, t DS, t DH and tCPW should be satisfied by both UWE and LWE.
11
HM514170C, HM51S4170C Series
22. When out put buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH (min)/VIL(max) level. 23. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 24. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 s interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 25. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 26. H or L (H: VIH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) Invalid Dout
12
HM514170C, HM51S4170C Series
Notes concerning 2WE control
Please do not separate the U W E/LWE operation timing intentionally. UWE/LWE are allowed under the following conditions. However skew between
(1) Each of the UWE/LWE should satisfy the timing specifications individually. (2) Different operation mode for upper/lower byte is not allowed; such as following.
RAS
CAS
Delayed write
LWE
Early write
UWE
(3) Closely separated upper/lower byte control is not allowed. Unless the condition (tCP tUL) is satisfied.
RAS
LWE
UWE
t UL
13
HM514170C, HM51S4170C Series
Timing Waveforms *26
Read Cycle
t RC t RAS
RAS tT t RCD t CSH t RSH t CAS t RP t CRP
CAS t ASR t RAD t RAH t ASC t RAL t CAH
Address
Row
Column
t RCS UWE LWE t CAC t AA High-Z Dout t RAC t DZC Din High-Z t OAC
t RCH
t RRH t OFF1
Dout t OFF2 t CDD
t ODD t DZO
OE
14
HM514170C, HM51S4170C Series
Early Write Cycle
t RC t RAS
RAS tT t RCD t CSH CAS t RSH t CAS t CRP
t RP
t ASR t RAH t ASC t CAH
Address
Row
Column
t WCS UWE LWE
t WCH
t DS
t DH
Din
Din
Dout
High-Z
* OE : H or L
15
HM514170C, HM51S4170C Series
Delayed Write Cycle
t RC t RAS t RP
RAS t CSH tT t RCD CAS t ASC t RAH t CAH Column t RSH t CAS t ASR t CWL t RWL t CRP
Address
Row
t RCS
t WP
UWE LWE t DH t DS
Din t DZC t DZO Dout High-Z t COD Invalid Dout* t OFF2 OE
*
Din t ODD t OEH
* Do not enable Dout during delayed write cycle.
Read-Modify-Write Cycle
16
HM514170C, HM51S4170C Series
t RWC tT t RP
RAS t CRP t RCD CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWL t CWD t AWD t WP t RWL
UWE LWE t RWD
t AA
t CAC t RAC t DZC Din High-Z t DS
t DH
Din
Dout
High-Z t OAC
Dout t OFF2 t DZO t ODD
t OEH
OE
17
HM514170C, HM51S4170C Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP CAS t RPC t CRP
t RAH t ASR Address Row
Dout
High-Z
* UWE, LWE and OE : H or L ** Refresh address : A0 - A9 (AX0 - AX9)
18
HM514170C, HM51S4170C Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS ** t RP t RC t RAS** t RP
RAS tT t RPC t CPN CAS t RPC t CSR t CHR t CPN t CSR t CHR t CRP
Address
t OFF1 Dout High-Z
* UWE, LWE : H or L ** Do not extend tRAS tRAS (max). Untested self refresh mode may be activated and loss of data may be resulted. (HM514170C)
19
HM514170C, HM51S4170C Series
Fast Page Mode Read Cycle
t RASC t RHCP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RP
CAS t RAD t ASR t RAH t ASC t CAH t ASC t RAL t ASC t CAH
t CAH
Address
Row
Column t RCS t RCS t RCH
Column t RCS t RCH
Column t RRH t RCH
UWE LWE t DZC High-Z t ODD t CAC t AA t RAC t OFF1 Dout High-Z t DZO t OAC t DZO t OFF2 OE Dout t AA t ACP t OFF1 t CDD t DZC t CDD High-Z t CAC High-Z t CAC t AA t ACP t DZO Dout t ODD t OFF2 t OAC t OFF2 t OFF1 t ODD t DZC
t CDD
Din
Dout
t OAC
20
HM514170C, HM51S4170C Series
Fast Page Mode Early Write Cycle
t RASC
t RP
RAS t CSH tT t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
CAS
t ASR
t RAH
t ASC
t CAH
t ASC
t CAH
t ASC
t CAH
Address
Row
Column t WCS t WCH
Column t WCS t WCH t WCS
Column
t WCH
UWE LWE t DS t DS t DH t DH t DS t DH
Din
Din
Din
Din
Dout
High-Z
* OE
: H or L
21
HM514170C, HM51S4170C Series
Fast Page Mode Delayed Write Cycle
t RASC t RP
RAS t CSH tT t RCD CAS t ASR t RAH t ASC t CAH t ASC t CAH t CWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t ASC t CAH
Address
Row
Column t CWL t RCS t WP
Column
Column t CWL t WP t WP t RWL
UWE LWE t DH t DS t RCS t DS t DH t RCS t DS t DH
Din
Din
Din
Din t OEH
Dout t ODD
High-Z
OE
22
HM514170C, HM51S4170C Series
Fast Page Mode Read-Modify-Write Cycle
t RP
t RASC RAS t RCD tT CAS t RAD t RAH t ASR t CAH t ASC t ASC Column t CWL t WP t RCS t AWD t CWD t CPW t WP t RCS t CWL t ACP t CAH t CAH t ASC t CP t PCM t CP
t CRP
Address
Row
Column t AWD t CWD t RWD
Column t CPW t AWD t CWD t CWL t RWL t WP
t RCS
UWE LWE t DS t DZC t CAC t DH t DZC t CAC t DS t DH t ACP t DZC High-Z t CAC t OEH t OAC Dout t OFF2 t DZO t OEH t DS t DH
Din
High-Z t AA t RAC t OAC
Din t DZO t OEH
High-Z t AA t OAC Dout t OFF2
Din
Din
Dout
High-Z
Dout t OFF2
t DZO
OE t ODD t ODD t ODD
23
HM514170C, HM51S4170C Series
Self Refresh Cycle
t RP
t RASS
t RPS
RAS tT t RPC t CPN CAS t CRP t CSR t CHS
Address
t OFF1 Dout High-Z
* UWE, LWE and OE : H or L
The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1. Please do not use t RASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of tRP. 2. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 s interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 4. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self-refresh mode, all memory cells need to be refreshed before reentering the self refresh mode again.
24
HM514170C, HM51S4170C Series
Package Dimensions
HM51(S)4170CJ/CLJ Series (CP-40DA)
Unit: mm
25.80 26.16 Max 40 21 10.16 0.13 0.74
1.30 Max 3.50 0.26
1
20
11.18 0.13
0.43 0.10
1.27 0.10
0.80
9.40 0.25
25
2.85 0.12
+0.25 -0.17
HM514170C, HM51S4170C Series
HM51(S)4170CTT/CLTT Series (TTP-44/40DB)
Unit: mm
44
18.41 18.81 Max 35 32
23
1
10 13 0.80 0.13 M 1.005 Max
22
0.27 0.07
10.16
11.76 0.20 0 - 5 0.13 0.05
+0.075 -0.025
1.20 Max
0.10
0.145
0.50 0.10
26
0.68
0.80

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